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DS1350W
POWER-DOWN/POWER-UP TIMING
(T A : See Note 10)
PARAMETER
V C C Fail Detect to CE and
WE Inactive
SYMBOL
t PD
MIN
TYP
MAX
1.5
UNITS
μs
NOTES
11
V CC slew from V TP to 0V
t F
150
μs
V CC Fail Detect to RST
Active
V CC slew from 0V to V TP
V CC Valid to CE and WE
Inactive
V CC Valid to End of Write
Protection
t RPD
t R
t PU
t REC
150
15
2
125
μs
μs
ms
ms
14
V CC Valid to RST Inactive
V CC Valid to BW Valid
t RPU
t BPU
150
200
350
1
ms
s
14
14
BATTERY WARNING TIMING
(T A : See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Battery Test Cycle
Battery Test Pulse Width
Battery Test to BW Active
t BTC
t BTPW
t BW
24
1
1
hr
s
s
(T A = +25°C)
PARAMETER
Expected Data
Retention Time
SYMBOL
t DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = V IH or V IL . If OE = V IH during write cycle, the output buffers remain in a high impedance state.
3. t WP is specified as the logical AND of CE and WE . t WP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. t DS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1350W has a built-in switch that disconnects the lithium source until V CC is first applied by
the user. The expected t DR is defined as accumulative time in the absence of V CC starting from the
time power is first applied by the user.
8 of 10
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